1. Field of the Invention
Embodiments relate to a multi memory chip. More particularly, embodiments relate to a multi memory chip in which internal data transmission between memories is possible, a system including the same, and an associated method.
2. Description of the Related Art
Due to the growth of semiconductor integrated technology, a multi core Central Processing Unit (CPU) including a plurality of CPU cores in one chip has been developed and a multi memory chip including a plurality of memories in one chip has also been developed. In addition, in order to provide high-speed and low-speed operations, a method of stacking a multi memory chip on the multi core CPU may be used.
When stacking a multi memory chip on the multi core CPU, a number of input/output pins is not limited as compared with separately packaging the multi memory chip and the multi core CPU. In addition, stacking a multi memory chip on the multi core CPU rapidly decreases a parasitic resistance, a parasitic inductance, and a parasitic capacitance. Thus, both high-speed and low-speed operations may be realized.
FIG. 1 illustrates a schematic diagram of a conventional stacking of a multi memory chip 11 on a multi core CPU 13.
Referring to FIG. 1, the multi memory chip 11 includes a plurality of memories M1-M6, and the multi core CPU 13, including a plurality of CPU cores CORE1-CORE6, is stacked with the multi memory chip 11. The CPU cores CORE1-CORE6 in the multi core CPU 13 operate independently, and respectively correspond to the memories M1-M6 of the multi memory chip 11. For example, the CPU core CORE2 corresponds to the memory ME2, and the memory ME2 is only controlled by the CPU core CORE2, and so forth.
In applications, e.g., multi-media, it may be desirable to transmit data from one of the memories to another one of the memories. For example, as illustrated in FIG. 1, when data should be transmitted from the memory M1 to the memory M2, data is first transmitted from the memory M1 to the CPU core CORE1 corresponding to the memory M1. Then, data is transmitted from the CPU core CORE1 to the CPU core CORE2 corresponding to the memory M2. Finally, data is transmitted from the CPU core CORE2 to the memory M2.
As illustrated in FIG. 1, the data transmission requires numerous steps. Thus, a transmission data path is lengthened, increasing data transmission time and latency.